VHDL

Etude sur la création d'un micro-processeur en traitement du signal :

Conception d'un microprocesseur avec des FPGA. Grâce au language VHDL on peut concevoir des fonctions basées sur des portes logiques. Le but de cette page est de vous montrer quels sont les programmes pour créer un micro-processeur pour du traitement du signal.

Création d'une bibliothèque de composants.

--fichier composant.vhdl library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_signed.all; package composants_L3_2007 is component add8 port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end component; component sub8 port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); signe : out std_logic); end component; component mul8 port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end component; component shl8 port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end component; component shr8 port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end component; component max8 port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end component; component min8 port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end component; component comp8 port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(8 downto 0)); end component; component mux8 port( y0,y1,y2,y3,y4,y5,y6 : in std_logic_vector(8 downto 0); s : out std_logic_vector(8 downto 0); x : in std_logic_vector(2 downto 0)); end component; component mux16 port( y0,y1,y2,y3,y4 : in std_logic_vector(15 downto 0); s : out std_logic_vector(15 downto 0); x : in std_logic_vector(2 downto 0)); end component; component reg16 port( D: in std_logic_vector(15 downto 0); Q : out std_logic_vector(15 downto 0); clk, raz : in std_logic); end component; component regadr port( D: in std_logic_vector(5 downto 0); Q : out std_logic_vector(5 downto 0); clk, raz, cmde : in std_logic); end component; component regins port( D : in std_logic_vector(29 downto 0); muins : out std_logic_vector(23 downto 0); adrins : out std_logic_vector(5 downto 0); clk : in std_logic); end component; end composants_L3_2007; ------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity add8 is port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end add8; architecture add8_arch of add8 is signal calc : std_logic_vector(8 downto 0); begin calc(7 downto 0) <= x + y; s<= calc(7 downto 0); c <= '0'; end add8_arch; ------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity sub8 is port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); signe : out std_logic); end sub8; architecture sub8_arch of sub8 is signal calc : std_logic_vector(8 downto 0); begin calc(7 downto 0) <= x - y; s<= calc(7 downto 0); signe <= '0' when x>y else '1'; end sub8_arch; ------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity shl8 is port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end shl8; architecture shl8_arch of shl8 is begin s <= shl(x,y); c<='0'; end shl8_arch; ------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity shr8 is port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end shr8; architecture shr8_arch of shr8 is begin s <= shr(x,y); c<='0'; end shr8_arch; ------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity max8 is port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end max8; architecture max8_arch of max8 is begin s<= x when x > y else y; c<= '0'; end max8_arch; ------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity min8 is port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(7 downto 0); c : out std_logic); end min8; architecture min8_arch of min8 is begin s<= x when x < y else y; c<='0'; end min8_arch; ------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity comp8 is port( x,y : in std_logic_vector(7 downto 0); s : out std_logic_vector(8 downto 0)); end comp8; architecture comp8_arch of comp8 is begin s<= "000000001" when (x > y) else "000000010" when (x = y) else "000000100" when (x < y) else "000000000"; end comp8_arch; ------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.STD_LOGIC_arith.all; use work.composants_L3_2007.all; entity mux8 is port( y0,y1,y2,y3,y4,y5,y6 : in std_logic_vector(8 downto 0); s : out std_logic_vector(8 downto 0); x : in std_logic_vector(2 downto 0)); end mux8; architecture mux8_arch of mux8 is begin s<= y0 when x = "000" else y1 when x = "001" else y2 when x = "010" else y3 when x = "011" else y4 when x = "100" else y5 when x = "101" else y6 when x = "110" else "000000000" when x = "111"; end mux8_arch; ------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.STD_LOGIC_arith.all; use work.composants_L3_2007.all; entity mux16 is port( y0,y1,y2,y3,y4 : in std_logic_vector(15 downto 0); s : out std_logic_vector(15 downto 0); x : in std_logic_vector(2 downto 0)); end mux16; architecture mux16_arch of mux16 is begin s<= y0 when x = "000" else y1 when x = "001" else y2 when x = "010" else y3 when x = "011" else y4 when x = "100" else "0000000000000000"; end mux16_arch; ------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.STD_LOGIC_arith.all; use work.composants_L3_2007.all; entity reg16 is port( D : in std_logic_vector(15 downto 0); Q : out std_logic_vector(15 downto 0); clk, raz : in std_logic); end reg16; architecture reg16_arch of reg16 is begin process(clk) begin if (raz = '1') then Q <= "0000000000000000"; elsif rising_edge(clk) then Q<=D; end if; end process; end reg16_arch; ------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.STD_LOGIC_arith.all; use work.composants_L3_2007.all; entity regadr is port(D : in std_logic_vector(5 downto 0); Q : out std_logic_vector(5 downto 0); clk, raz, cmde : in std_logic); end regadr; architecture regadr_arch of regadr is begin process(clk,raz) begin if (raz = '1') then Q <= "000000"; elsif (rising_edge(clk)and(cmde = '1')) then Q<=D; end if; end process; end regadr_arch; ------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.STD_LOGIC_arith.all; use work.composants_L3_2007.all; entity regins is port(D : in std_logic_vector(29 downto 0); muins : out std_logic_vector(23 downto 0); adrins : out std_logic_vector(5 downto 0); clk : in std_logic); end regins; architecture regins_arch of regins is begin process(clk) begin if falling_edge(clk) then muins <= D(23 downto 0); adrins <= D(29 downto 24); end if; end process; end regins_arch; ------------------------------------------------------

Création d'une bibliothèque de composants.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.STD_LOGIC_arith.all; use work.composants_L3_2007.all; entity ALU is Port ( a,b : in std_logic_vector(7 downto 0); sel : in std_logic_vector(2 downto 0); s : out std_logic_vector(8 downto 0)); end ALU; architecture ALU_arch of ALU is signal e0,e1,e2,e3,e4,e5,e6 : std_logic_vector(8 downto 0); signal mas : std_logic; begin mas<='0'; U1: add8 port map(a,b,s=>e0(7 downto 0),c=>e0(8)); U2: sub8 port map(a,b,s=>e1(7 downto 0),signe=>e1(8)); U3: shl8 port map(a,b,s=>e2(7 downto 0),c=>e2(8)); U4: shr8 port map(a,b,s=>e3(7 downto 0),c=>e3(8)); U5: max8 port map(a,b,s=>e4(7 downto 0),c=>e4(8)); U6: min8 port map(a,b,s=>e5(7 downto 0),c=>e5(8)); U7: comp8 port map(a,b,s=>e6); U8: mux8 port map(e0,e1,e2,e3,e4,e5,e6, s,sel); end ALU_arch;

Création de la partie opérative

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.composants_L3_2007.all; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity partie_op is Port ( x,d : in std_logic_vector(7 downto 0); mux1, mux2,C : in std_logic_vector(2 downto 0); lda,ldb,lds,ldq,razq : in std_logic; y : out std_logic_vector(15 downto 0)); end partie_op; architecture Behavioral of partie_op is component alu port(a,b : in std_logic_vector(7 downto 0); sel : in std_logic_vector(2 downto 0); s : out std_logic_vector(8 downto 0)); end component; signal smu1,smu2,sa,sb,sp,ss,sq1,sq2,sq3 : std_logic_vector(15 downto 0); begin alu1 : alu port map( a => sa(7 downto 0), b => sb(7 downto 0), sel => C, s => sp(8 downto 0)); sp(15 downto 9) <= "0000000"; mu1 : mux16 port map( y0 => sq1, y1 => sq2, y2 => sq3, y3(7 downto 0) => d,y3(15 downto 8) => "00000000", y4(7 downto 0) => x,y4(15 downto 8) => "00000000", x => mux1, s => smu1); mu2 : mux16 port map( y0 => sq3, y1 => sq2, y2 => sq1, y3 => ss, y4 => sp, x => mux2, s => smu2); rega : reg16 port map( D => smu1, Q => sa, clk => lda, raz => '0'); regb : reg16 port map( D => smu2, Q => sb, clk => ldb, raz => '0'); regs : reg16 port map( D => sp, Q => ss, clk => lds, raz => '0'); regq1 : reg16 port map( D => ss, Q => sq1, clk => ldq, raz => razq); regq2 : reg16 port map( D => sq1, Q => sq2, clk => ldq, raz => razq); regq3 : reg16 port map( D => sq2, Q => sq3, clk => ldq, raz => razq); y <= sq1; end Behavioral;

Création de la partie séquenceur

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.composants_L3_2007.all; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity sequenceur is Port ( clk, raz, cmde : in std_logic; inst : out std_logic_vector(23 downto 0)); end sequenceur; architecture Behavioral of sequenceur is signal adradr, adrsui : std_logic_vector(5 downto 0); signal srom : std_logic_vector(29 downto 0); type rom is array (0 to 6) of std_logic_vector (29 downto 0); -- addrsui & mu1 & mu2 & ld:ABSQ & razq & C & NC & d signal rom_tab: rom := ( "000001"& "100"& "010" & "0000"& "1" & "001"& "00"& "00000000", --charge x devant regA et 0 devant regB "000010"& "100"& "010" & "1100"& "0" & "001"& "00"& "00000000", --calcul de "x(t) - x(t-1)" puis result devant regS "000011"& "100"& "010" & "0010"& "0" & "001"& "00"& "00000000", --regS recopie sont entrée (x) "000100"& "100"& "010" & "0001"& "0" & "001"& "01"& "00000000", -- fait sortir la valeur "000101"& "100"& "010" & "0000"& "1" & "001"& "00"& "00000000", -- "000110"& "100"& "010" & "0100"& "0" & "001"& "00"& "00000000", "000001"& "100"& "011" & "0010"& "0" & "001"& "00"& "00000000" ); begin srom <= rom_tab(conv_integer(adradr)); adr : regadr port map( cmde => cmde, raz => raz, clk => clk, D => adrsui, Q => adradr); ins : regins port map( clk => clk, D => srom, adrins => adrsui, muins => inst); end Behavioral;

Création du micro-processeur

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity tp_dsp is port(clk, raz, cmde : in std_logic; y : out std_logic_vector(15 downto 0); x : in std_logic_vector(7 downto 0); f : out std_logic ); end tp_dsp; architecture Behavioral of tp_dsp is component partie_op port( x,d : in std_logic_vector(7 downto 0); mux1, mux2,C : in std_logic_vector(2 downto 0); lda,ldb,lds,ldq,razq : in std_logic; y : out std_logic_vector(15 downto 0)); end component; component sequenceur port(clk, raz, cmde : in std_logic; inst : out std_logic_vector(23 downto 0)); end component; signal instruc : std_logic_vector(23 downto 0); begin seq : sequenceur port map( cmde => cmde, raz => raz, clk => clk, inst => instruc); parop : partie_op port map( x => x, d => instruc(7 downto 0), C => instruc(12 downto 10), razq => instruc(13), ldq => instruc(14), lds => instruc(15), ldb => instruc(16), lda => instruc(17), mux2 => instruc(20 downto 18), mux1 => instruc(23 downto 21), y => y); f <= instruc(8); end Behavioral;